NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_18

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_EMC_18

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc

1 (ALT1): Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1

2 (ALT2): Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2

3 (ALT3): Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO22 of instance: flexio1

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_18

Links

() ()